peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 88

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

4.1.2
The Receive Address Low/High Bytes (registers
masked on a per bit basis by setting the corresponding bits in the mask registers
AMRAL1/AMRAH1
recognition. Masked bit positions always match in comparison of the received frame
address with the respective address fields in the Receive Address Low/High registers.
This feature is applicable to all HDLC protocol modes with address recognition (auto
mode, address mode 2 and address mode 1). It is disabled if all bits of mask bit fields
AMRAL1/AMRAH1
Detection of the fixed group address FE
mode, remains unchanged.
As an option in the auto mode, address mode 2 and address mode 1, the 8/16 bit
address field of received frames can be pushed to the receive data buffer (first one/two
bytes of the frame). This function is especially useful in conjunction with the extended
broadcast address recognition. It is enabled by setting control bit ’RADD’ in register
CCR3H.
4.1.3
Two different types of frames can be transmitted:
– I-frames and
– transparent frames
as shown below.
Data Sheet
Receive Address Handling
HDLC Transmit Data Processing
and
and AMRAL2/AMRAH2. This allows extended broadcast address
AMRAL2/AMRAH2
H
or FC
88
are set to ‘zero’ (which is the reset value).
H
, if applicable to the selected operating
RAL1/RAH1
Detailed Protocol Description
and RAL2/RAH2) can be
PEB 20525
PEF 20525
2000-09-14