peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 127

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
Register 14
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
MRBFB
MRBFA
MRDTEB
MRDTEA
MTDTEB
MTDTEA
Bit
7
0
Mask Receive Buffer Full Interrupt Channel B
Mask Receive Buffer Full Interrupt Channel A
Mask Receive DMA Transfer End Interrupt Channel B
Mask Receive DMA Transfer End Interrupt Channel A
Mask Transmit DMA Transfer End Interrupt Channel B
Mask Transmit DMA Transfer End Interrupt Channel A
If a bit in this interrupt mask register is set to ’1’, the corresponding
interrupt is not generated and not indicated in the corresponding bit
position in the
MRBFB
DIMR
DMA Interrupt Mask Register
6
read/write
77
0F
H
H
MRDTEB MTDTEB
DISR
5
DMA Interrupt Mask Register
register. After reset all interrupts are masked.
5-127
4
3
0
Register Description (DIMR)
MRBFA
2
MRDTEA MTDTEA
1
PEB 20525
PEF 20525
2000-09-14
0