peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 166

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

Data Sheet
The following register bit fields allow flexible assignment of bit- or octet-aligned transmit
time-slots to the serial channel. For more detailed information refer to chapters
Mode 5a (Time Slot Mode)” on Page 56
on Page
TCS(2:0)
TEPCM
TTSN(6:0)
TCC(8:0)
63.
Transmit Clock Shift
This bit field determines the transmit clock shift.
Enable PCM Mask Transmit
This bit selects the additional Transmit PCM Mask (refer to register
PCMTX0..PCMTX3):
TEPCM=’0’
TEPCM=’1’
Transmit Time Slot Number
This bit field selects the start position of the timeslot in time-slot
configuration mode (clock mode 5a/5b):
Offset = 1+TTSN*8 + TCS (1..1024 clocks)
Transmit Channel Capacity
This bit field determines the transmit time-slot width in standard time-slot
configuration (bit TEPCM=’0’):
Number of bits = TCC + 1, (1..512 bits/time-slot)
Standard time-slot configuration.
The time-slot width is constant 8 bit, bit fields ’TTSN’ and
’TCS’ determine the offset of the PCM mask and ’TCC’ is
ignored. Each time-slot selected via register
PCMTX0..PCMTX3
5-166
and
“Clock Mode 5b (Octet Sync Mode)”
is an active transmit timeslot.
Register Description (TTSA3)
PEB 20525
PEF 20525
2000-09-14
“Clock