peb20525 Infineon Technologies Corporation, peb20525 Datasheet - Page 68

• Manufacturer Part Number: peb20525
• Description: 2 Channel Serial Optimized Communication Controller For Hdlc/ppp
• Manufacturer: Infineon Technologies Corporation

3.2.4
Each serial channel provides a baud rate generator (BRG) whose division factor is
controlled by registers
depends on the selected clock mode.
Table 9
Register Bit-Fields
Offset
BRRL
38
BRRH
39
The clock division factor k is calculated by:
3.2.5
The SCC offers the advantage of recovering the received clock from the received data
by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock
information via a separate serial clock line. For this purpose, the DPLL is supplied with
a ‘reference clock’ from the BRG which is 16 times the expected data clock rate (clock
mode 2, 3a, 6, 7a). The transmit clock may be obtained by dividing the output of the BRG
by a constant factor of 16 (clock mode 2b, 6b; bit ’SSEL’ in register
directly from the DPLL (clock mode 3a, 7a).
The main task of the DPLL is to derive a receive clock and to adjust its phase to the
incoming data stream in order to enable optimal bit sampling.
The mechanism for clock recovery depends on the selected data encoding (see
Encoding” on Page
The following functions have been implemented to facilitate a fast and reliable
synchronization:
Data Sheet
H
H
/88
/89
H
H
Pos.
5..0
11..8
Baud Rate Generator (BRG)
Clock Recovery (DPLL)
BRRL/BRRH Register and Bit-Fields
Name
BRN
BRM
74).
BRRL
and BRRH. Whether the BRG is in the clocking path or not
Default
0
0
k
f
=
BRG
(
N
68
+
=
1
f
in
)
Description
Baud Rate Factor N
range N = 0..63
Baud Rate Factor M,
range M = 0..15
´
k ¤
2
M
Functional Overview
CCR0L
PEB 20525
PEF 20525
set) or also
2000-09-14
“Data