LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 137

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type R/W1C, reset 0x0000.0000
November 30, 2007
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
RO
RO
30
14
0
0
RTCALT1
RTCALT0
LOWBAT
reserved
EXTW
Name
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W1C
R/W1C
R/W1C
R/W1C
RO
RO
Type
27
11
0
0
RO
RO
RO
26
10
0
0
0x000.0000
reserved
Reset
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
External Wake-Up Masked Interrupt Clear
Reads return an indeterminate value.
Low Battery Voltage Masked Interrupt Clear
Reads return an indeterminate value.
RTC Alert1 Masked Interrupt Clear
Reads return an indeterminate value.
RTC Alert0 Masked Interrupt Clear
Reads return an indeterminate value.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
LM3S2965 Microcontroller
R/W1C
EXTW
RO
19
0
3
0
LOWBAT
R/W1C
RO
18
0
2
0
RTCALT1
R/W1C
RO
17
0
1
0
RTCALT0
R/W1C
RO
16
0
0
0
137