LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 222

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

General-Purpose Timers
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Timer2 base: 0x4003.2000
Timer3 base: 0x4003.3000
Offset 0x00C
Type R/W, reset 0x0000.0000
222
Reset
Reset
Type
Type
Bit/Field
31:15
14
13
12
reserved
RO
RO
31
15
0
0
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall and the output trigger. The output
trigger can be used to initiate transfers on the ADC module.
TBPWML
R/W
RO
30
14
0
0
TBPWML
reserved
reserved
TBOTE
Name
TBOTE
R/W
RO
29
13
0
0
reserved
RO
RO
28
12
0
0
R/W
RO
Type
27
11
R/W
R/W
0
0
RO
RO
TBEVENT
R/W
RO
26
10
0
0
Reset
0x00
TBSTALL
0
0
0
R/W
RO
25
0
9
0
Preliminary
TBEN
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
GPTM TimerB Output Trigger Enable
The TBOTE values are defined as follows:
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
RO
Value
Value
24
0
8
0
reserved
0
1
0
1
reserved
Description
Output is unaffected.
Output is inverted.
Description
The output TimerB trigger is disabled.
The output TimerB trigger is enabled.
RO
RO
23
0
7
0
TAPWML
R/W
RO
22
0
6
0
TAOTE
R/W
RO
21
0
5
0
RTCEN
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
TAEVENT
November 30, 2007
R/W
RO
18
0
2
0
TASTALL
R/W
RO
17
0
1
0
TAEN
R/W
RO
16
0
0
0