LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 384

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LM3S2965-IRN50-A1T

Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
Inter-Integrated Circuit (I
384
Figure 15-11. Master Burst RECEIVE after Burst SEND
2
C) Interface
Master Transmit mode
STOP condition is not
Master Receive mode
Master operates in
Master operates in
Write ---01011 to
Write Slave
Address to
generated
I2CMCS
I2CMSA
Idle
Idle
Preliminary
condition is generated
with changing data
Repeated START
direction
November 30, 2007

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