LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 223

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

November 30, 2007
Bit/Field
11:10
9
8
7
6
5
TBEVENT
TBSTALL
TAPWML
reserved
TAOTE
Name
TBEN
Type
R/W
R/W
R/W
R/W
R/W
RO
Reset
0x0
0
0
0
0
0
Preliminary
Description
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
GPTM TimerB Stall Enable
The TBSTALL values are defined as follows:
GPTM TimerB Enable
The TBEN values are defined as follows:
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerA PWM Output Level
The TAPWML values are defined as follows:
GPTM TimerA Output Trigger Enable
The TAOTE values are defined as follows:
Value
Value
Value
Value
Value
0x0
0x1
0x2
0x3
0
1
0
1
0
1
0
1
Description
Positive edge.
Negative edge.
Reserved
Both edges.
Description
TimerB stalling is disabled.
TimerB stalling is enabled.
Description
TimerB is disabled.
TimerB is enabled and begins counting or the capture logic is
enabled based on the GPTMCFG register.
Description
Output is unaffected.
Output is inverted.
Description
The output TimerA trigger is disabled.
The output TimerA trigger is enabled.
LM3S2965 Microcontroller
223