LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 492
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LM3S2965-IRN50-A1T
Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IRN50-A1T.pdf
(574 pages)
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Pulse Width Modulator (PWM)
492
Bit/Field
9:8
7:6
5:4
3:2
ActCmpBU
ActCmpAD
ActCmpAU
ActLoad
Name
Type
R/W
R/W
R/W
R/W
Reset
0x0
0x0
0x0
0x0
Preliminary
Description
Action for Comparator B Up
The action to be taken when the counter matches comparator B while
counting up. Occurs only when the Mode bit in the PWMnCTL register
(see page 481) is set to 1.
The table below defines the effect of the event on the output signal.
Action for Comparator A Down
The action to be taken when the counter matches comparator A while
counting down.
The table below defines the effect of the event on the output signal.
Action for Comparator A Up
The action to be taken when the counter matches comparator A while
counting up. Occurs only when the Mode bit in the PWMnCTL register
is set to 1.
The table below defines the effect of the event on the output signal.
Action for Counter=Load
The action to be taken when the counter matches the load value.
The table below defines the effect of the event on the output signal.
Value
Value
Value
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Description
Do nothing.
Invert the output signal.
Set the output signal to 0.
Set the output signal to 1.
Description
Do nothing.
Invert the output signal.
Set the output signal to 0.
Set the output signal to 1.
Description
Do nothing.
Invert the output signal.
Set the output signal to 0.
Set the output signal to 1.
Description
Do nothing.
Invert the output signal.
Set the output signal to 0.
Set the output signal to 1.
November 30, 2007
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