LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 290

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Analog-to-Digital Converter (ADC)
ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1)
Base 0x4003.8000
Offset 0x060
Type RO, reset 0x0000.0000
290
Reset
Reset
Type
Type
Bit/Field
31:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
RO
RO
31
15
0
0
reserved
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1),
offset 0x060
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2),
offset 0x080
This register defines the analog input configuration for each sample in a sequence executed with
Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible
samples. See the ADCSSMUX0 register on page 283 for detailed bit descriptions.
RO
RO
30
14
0
0
reserved
reserved
reserved
reserved
Name
MUX3
MUX2
MUX1
MUX0
R/W
RO
29
13
0
0
MUX3
R/W
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
0
0
RO
RO
RO
RO
reserved
RO
RO
26
10
0
0
Reset
0x00
0
0
0
0
0
0
0
R/W
RO
25
0
9
0
Preliminary
MUX2
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4th Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
3rd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
2nd Sample Input Select
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1st Sample Input Select
R/W
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
reserved
RO
RO
22
0
6
0
R/W
RO
21
0
5
0
MUX1
R/W
RO
20
0
4
0
RO
RO
19
0
3
0
reserved
November 30, 2007
RO
RO
18
0
2
0
R/W
RO
17
0
1
0
MUX0
R/W
RO
16
0
0
0