LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 514

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Quadrature Encoder Interface (QEI)
QEI Interrupt Enable (QEIINTEN)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x020
Type R/W, reset 0x0000.0000
514
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020
This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to
the controller if its corresponding bit in this register is set to 1.
RO
RO
30
14
0
0
reserved
IntTimer
IntIndex
IntError
Name
IntDir
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
R/W
R/W
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
reserved
Reset
0x00
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Interrupt Enable
When 1, an interrupt occurs when a phase error is detected.
Direction Change Interrupt Enable
When 1, an interrupt occurs when the direction changes.
Timer Expires Interrupt Enable
When 1, an interrupt occurs when the velocity timer expires.
Index Pulse Detected Interrupt Enable
When 1, an interrupt occurs when the index pulse is detected.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
IntError
R/W
RO
19
0
3
0
November 30, 2007
IntDir
R/W
RO
18
0
2
0
IntTimer
R/W
RO
17
0
1
0
IntIndex
R/W
RO
16
0
0
0