LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 425

no-image

LM3S2965-IRN50-A1T

Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
November 30, 2007
Bit/Field
3
2
1
0
Name
INIT
EIE
SIE
IE
Type
R/W
R/W
R/W
R/W
Reset
0
0
0
1
Preliminary
Description
Error Interrupt Enable
0: Disabled. No Error Status interrupt is generated.
1: Enabled. A change in the Boff or EWarn bits in the CANSTS register
generates an interrupt.
Status Change Interrupt Enable
0: Disabled. No Status Change interrupt is generated.
1: Enabled. An interrupt is generated when a message has successfully
been transmitted or received, or a CAN bus error has been detected. A
change in the TxOk or RxOk bits in the CANSTS register generates an
interrupt.
CAN Interrupt Enable
0: Interrupt disabled.
1: Interrupt enabled.
Initialization
0: Normal operation.
1: Initialization started.
LM3S2965 Microcontroller
425

Related parts for LM3S2965-IRN50-A1T