LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 17

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Synchronous Serial Interface (SSI) ............................................................................................ 338
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Inter-Integrated Circuit (I
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Controller Area Network (CAN) Module ..................................................................................... 410
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November 30, 2007
SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 350
SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 352
SSI Data (SSIDR), offset 0x008 ...................................................................................... 354
SSI Status (SSISR), offset 0x00C ................................................................................... 355
SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 357
SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 358
SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 360
SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 361
SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 362
SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 363
SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 364
SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 365
SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 366
SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 367
SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 368
SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 369
SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 370
SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 371
SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 372
SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 373
SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 374
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
I
CAN Control (CANCTL), offset 0x000 ............................................................................. 424
CAN Status (CANSTS), offset 0x004 ............................................................................... 426
CAN Error Counter (CANERR), offset 0x008 ................................................................... 429
CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 430
CAN Interrupt (CANINT), offset 0x010 ............................................................................. 432
CAN Test (CANTST), offset 0x014 .................................................................................. 433
CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 435
2
2
2
2
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2
C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 389
C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 390
C Master Data (I2CMDR), offset 0x008 ......................................................................... 394
C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 395
C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 396
C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 397
C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 398
C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 399
C Master Configuration (I2CMCR), offset 0x020 ............................................................ 400
C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 402
C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 403
C Slave Data (I2CSDR), offset 0x008 ........................................................................... 405
C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 406
C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 407
C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 408
C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 409
2
C) Interface ........................................................................................ 375
Preliminary
LM3S2965 Microcontroller
17