LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 164
LM3S2965-IRN50-A1T
Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
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General-Purpose Input/Outputs (GPIOs)
9
9.1
164
General-Purpose Input/Outputs (GPIOs)
The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual
GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, and Port H). The GPIO module is
FiRM-compliant and supports 3-56 programmable input/output pins, depending on the peripherals
being used.
The GPIO module has the following features:
■
■
■
■
Functional Description
Important:
Each GPIO port is a separate hardware instantiation of the same physical block (see Figure
9-1 on page 165). The LM3S2965 microcontroller contains eight ports and thus eight of these physical
GPIO blocks.
Programmable control for GPIO interrupts
–
–
–
5-V-tolerant input/outputs
Bit masking in both read and write operations through address lines
Programmable control for GPIO pad configuration
–
–
–
–
–
Interrupt generation masking
Edge-triggered on rising, falling, or both
Level-sensitive on High or Low values
Weak pull-up or pull-down resistors
2-mA, 4-mA, and 8-mA pad drive
Slew rate control for the 8-mA drive
Open drain enables
Digital input enables
All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]).
The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1,
GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both
groups of pins back to their default state.
Preliminary
November 30, 2007
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