LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 429

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

CAN Error Counter (CANERR)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x008
Type RO, reset 0x0000.0000
November 30, 2007
Reset
Reset
Type
Type
Bit/Field
31:16
14:8
7:0
15
RO
RP
RO
31
15
0
0
Register 3: CAN Error Counter (CANERR), offset 0x008
This register contains the error counter values, which can be used to analyze the cause of an error.
RO
RO
30
14
0
0
reserved
Name
REC
TEC
RP
RO
RO
29
13
0
0
RO
RO
28
12
0
0
REC
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
RO
RO
26
10
0
0
0x0000
Reset
0x0
0x0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Received Error Passive
0: The Receive Error counter is below the Error Passive level (127 or
less).
1: The Receive Error counter has reached the Error Passive level (128
or greater).
Receive Error Counter
State of the receiver error counter (0 to 127).
Transmit Error Counter
State of the transmit error counter (0 to 255).
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
TEC
LM3S2965 Microcontroller
RO
RO
19
0
3
0
RO
RO
18
0
2
0
RO
RO
17
0
1
0
RO
RO
16
0
0
0
429