LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 437

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

CAN IF1 Command Mask (CANIF1CMSK)
CAN0 base: 0x4004.0000
CAN1 base: 0x4004.1000
Offset 0x024
Type RO, reset 0x0000.0000
November 30, 2007
Reset
Reset
Type
Type
Bit/Field
31:8
7
6
RO
RO
31
15
0
0
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084
The Command Mask registers specify the transfer direction and select which buffer registers are
the source or target of the data transfer.
RO
RO
30
14
0
0
reserved
WRNRD
Name
Mask
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
Type
27
11
R/W
R/W
0
0
RO
RO
RO
26
10
0
0
0x0000
Reset
0x0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Write, Not Read
0: Read. Transfer the message object address specified by the CAN
Command Request (CANIFnCRQ) register to the CAN message buffer
registers (CANIFnMSK1, CANIFnMSK2, CANIFnARB1, CANIFnARB2,
CANIFnCTL, CANIFnDA1, CANIFnDA2, CANIFnDB1, and
CANIFnDB2).
1: Write. Transfer data from the message buffer registers to the message
object address specified by the CANIFnCRQ register.
Access Mask Bits
When WRNRD=1 (writes):
0: Mask bits unchanged.
1: Transfer IDMask + Dir + MXtd to message object.
When WRNRD=0 (reads):
0: Mask bits unchanged.
1: Transfer IDMask + Dir + MXtd of the message object into the
Interface Registers.
RO
RO
24
0
8
0
reserved
WRNRD
R/W
RO
23
0
7
0
Mask
R/W
RO
22
0
6
0
R/W
RO
Arb
21
0
5
0
Control
R/W
RO
20
0
4
0
LM3S2965 Microcontroller
ClrIntPnd
R/W
RO
19
0
3
0
TxRqst/NewDat
R/W
RO
18
0
2
0
DataA
R/W
RO
17
0
1
0
DataB
R/W
RO
16
0
0
0
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