LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 25

no-image

LM3S2965-IRN50-A1T

Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
November 30, 2007
ARM FiRM-compliant Watchdog Timer
Controller Area Network (CAN)
Synchronous Serial Interface (SSI)
16-bit Timer modes
16-bit Input Capture modes
16-bit PWM mode
32-bit down counter with a programmable load register
Separate watchdog clock with an enable
Programmable interrupt generation logic with interrupt masking
Lock register protection from runaway software
Reset generation logic with an enable/disable
User-enabled stalling when the controller asserts the CPU Halt flag during debug
Supports CAN protocol version 2.0 part A/B
Bit rates up to 1Mb/s
32 message objects, each with its own identifier mask
Maskable interrupt
Disable automatic retransmission mode for TTCAN
Programmable loop-back mode for self-test operation
User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
ADC event trigger
General-purpose timer function with an 8-bit prescaler
Programmable one-shot timer
Programmable periodic timer
User-enabled stalling when the controller asserts CPU Halt flag during debug
ADC event trigger
Input edge count capture
Input edge time capture
Simple PWM mode with software-programmable output inversion of the PWM signal
Preliminary
LM3S2965 Microcontroller
25

Related parts for LM3S2965-IRN50-A1T