LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 504
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LM3S2965-IRN50-A1T
Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IRN50-A1T.pdf
(574 pages)
- Current page: 504 of 574
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Quadrature Encoder Interface (QEI)
19.4
Table 19-1. QEI Register Map
19.5
504
Offset
0x00C
0x01C
0x000
0x004
0x008
0x010
0x014
0x018
0x020
0x024
0x028
Name
QEICTL
QEISTAT
QEIPOS
QEIMAXPOS
QEILOAD
QEITIME
QEICOUNT
QEISPEED
QEIINTEN
QEIRIS
QEIISC
5.
6.
7.
Register Map
Table 19-1 on page 504 lists the QEI registers. The offset listed is a hexadecimal increment to the
register’s address, relative to the module’s base address:
■
■
Register Descriptions
The remainder of this section lists and describes the QEI registers, in numerical order by address
offset.
QEI0: 0x4002.C000
QEI1: 0x4002.D000
■
Enable the quadrature encoder by setting bit 0 of the QEICTL register.
Delay for some time.
Read the encoder position by reading the QEIPOS register value.
Write the QEIMAXPOS register with the value of 0x0000.0F9F.
R/W1C
Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
0x0000.0000
Reset
Preliminary
Description
QEI Control
QEI Status
QEI Position
QEI Maximum Position
QEI Timer Load
QEI Timer
QEI Velocity Counter
QEI Velocity
QEI Interrupt Enable
QEI Raw Interrupt Status
QEI Interrupt Status and Clear
November 30, 2007
page
See
505
507
508
509
510
511
512
513
514
515
516
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