LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 516

• Manufacturer Part Number: LM3S2965-IRN50-A1T
• Description: Microcontroller
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Quadrature Encoder Interface (QEI)
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
QEI1 base: 0x4002.D000
Offset 0x028
Type R/W1C, reset 0x0000.0000
516
Reset
Reset
Type
Type
Bit/Field
31:4
3
2
1
0
RO
RO
31
15
0
0
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. Bits set
to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question
has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding
interrupt reason.
RO
RO
30
14
0
0
reserved
IntTimer
IntIndex
IntError
Name
IntDir
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W1C
R/W1C
R/W1C
R/W1C
RO
RO
Type
27
11
0
0
RO
RO
RO
26
10
0
0
reserved
Reset
0x00
0
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Phase Error Interrupt
Indicates that a phase error was detected.
Direction Change Interrupt
Indicates that the direction has changed.
Velocity Timer Expired Interrupt
Indicates that the velocity timer has expired.
Index Pulse Interrupt
Indicates that the index pulse has occurred.
RO
RO
24
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
IntError
R/W1C
RO
19
0
3
0
R/W1C
November 30, 2007
IntDir
RO
18
0
2
0
IntTimer
R/W1C
RO
17
0
1
0
IntIndex
R/W1C
RO
16
0
0
0