LM3S2965-IRN50-A1T ETC2 [List of Unclassifed Manufacturers], LM3S2965-IRN50-A1T Datasheet - Page 355
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LM3S2965-IRN50-A1T
Manufacturer Part Number
LM3S2965-IRN50-A1T
Description
Microcontroller
Manufacturer
ETC2 [List of Unclassifed Manufacturers]
Datasheet
1.LM3S2965-IRN50-A1T.pdf
(574 pages)
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SSI Status (SSISR)
SSI0 base: 0x4000.8000
SSI1 base: 0x4000.9000
Offset 0x00C
Type RO, reset 0x0000.0003
November 30, 2007
Reset
Reset
Type
Type
Bit/Field
31:5
4
3
2
RO
RO
31
15
0
0
Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
RO
RO
30
14
0
0
reserved
Name
RNE
BSY
RFF
RO
RO
29
13
0
0
RO
RO
28
12
0
0
RO
RO
Type
27
11
0
0
RO
RO
RO
RO
reserved
RO
RO
26
10
0
0
Reset
0x00
0
0
0
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Busy Bit
The BSY values are defined as follows:
SSI Receive FIFO Full
The RFF values are defined as follows:
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
RO
RO
Value
Value
Value
24
0
8
0
reserved
0
1
0
1
0
1
Description
SSI is idle.
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
Description
Receive FIFO is not full.
Receive FIFO is full.
Description
Receive FIFO is empty.
Receive FIFO is not empty.
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
BSY
RO
RO
20
0
4
0
LM3S2965 Microcontroller
RFF
RO
RO
19
0
3
0
RNE
RO
RO
18
0
2
0
TNF
RO
RO
17
0
1
1
TFE
RO
R0
16
0
0
1
355
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