PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 115

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 1: SYSTEM Registers
PNX15XX_SER_3
Product data sheet
DCS DRAM Aperture Control Registers
Offset 0x06 3200
31:16
15:0
Offset 0x06 3204
31:16
15:0
Offset 0x06 3208
31:1
Bit
0
Symbol
DCS_DRAM_LO
Unused
DCS_DRAM_HI
Unused
Unused
DCS_DRAM_WE
2.4.1 DCS DRAM Aperture Control MMIO Registers
2.5 Aperture Boundaries
DCS_DRAM_LO
DCS_DRAM_HI
APERTURE_WE
The MMIO aperture is always 2 Megabytes.
The DRAM aperture size range is from 1 to 256 Megabytes. Defined at boot time, it
may be changed later on by the TM3260 CPU.
The XIO aperture size range is from 1 to 128 Megabytes.
Acces
s
R/W
-
R/W
-
-
R/W
Value
0x0000
-
0x0000
-
-
0x0
Rev. 3 — 17 March 2006
Description
DCS_DRAM_LO indicates the lowest DCS bus address mapped to
DRAM. Its granularity is of 64 Kilobytes.
The reset value is 0.
Writes to this register are controlled by the DCS_DRAM_WE bit in
the APERTURE_WE MMIO register.
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
DCS_DRAM_HI indicates the highest DCS bus address mapped to
DRAM. Its granularity is of 64 Kilobytes.
The reset value of 0 disables memory accesses from the DCS bus.
Writes to this register are controlled by the DCS_DRAM_WE bit in
the APERTURE_WE MMIO register.
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
• ‘0’: Writing to DCS_DRAM_LO or DCS_DRAM_HI is disabled.
• ‘1’: Writing to DCS_DRAM_LO or DCS_DRAM_HI is enabled.
• When writing to either DCS_DRAM_LO or DCS_DRAM_HI
• By default it is not authorized to write to the DCS_DRAM_LO and
• The address range defined by the content of DCS_DRAM_LO or
occurs, this bit is automatically cleared.
DCS_DRAM_HI registers.
DCS_DRAM_HI must not overlap the address ranges of the
other apertures on the DCS bus. This can happen temporarily
when changing either the DCS_DRAM_LO or the
DCS_DRAM_HI. Therefore any change of the DCS_DRAM_LO
or DCS_DRAM_HI registers must be done by first disabling the
DCS DRAM aperture. This is achieved by starting to change
DCS_DRAM_LO or DCS_DRAM_HI such that DCS_DRAM_LO
is greater than DCS_DRAM_HI.
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
3-6