PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 249

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 8: Registers Description
PNX15XX_SER_3
Product data sheet
Bit
Offset 0x04 0088
31:24
23:16
15:3
2
1
0
Offset 0x04 008C
31:24
20:16
11:8
7:3
2:0
Offset 0x04 0090
31:16
15:8
7:3
Symbol
upper_io3_addr
upper_io2_addr
Reserved
use_io3_addr
use_io2_addr
use_pcibase2_as_io
Reserved
slv_memrd_fetch
slv_threshold
Reserved
slv_mrmul_fetch
Reserved
dma_threshold
Reserved
PCI_IO
Slave DTL tuning
DMA DTL tuning
Acces
s
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R
R/W
R
R/W
R
Value
0
0
0
0
0
0
0
111
10
0
001
0
0x1B
0
Rev. 3 — 17 March 2006
Description
Bits [31:24] of IO address during PCI IO transactions.
Bits [23:16] of IO address during PCI IO transactions.
Use “upper_io3_addr” as the upper address for PCI IO transactions.
Use “upper_io3_addr” and “upper_io2_addr” as the upper address
for PCI IO transactions.
1: PCI_Base2 will forward PCI2 DTL transactions to PCI bus as IO
transactions. The address will unchanged or modified with an
alternate upper addresses selected above.
0: PCI_Base2 will forward PCI2 DTL transactions to PCI bus as
memory transactions with unchanged address.
PCI slave DTL read block size for memory read command. Default
value is 8 32-bit words. Maximum is 64 32-bit words.
Threshold (amount of data not consumed from previous read
request) for when PCI slave DTL requests more read data when
responding to memory read command. This must be set to a value
less than the smallest of slv_memrd_fetch, Cache Line Size or
read_block_siz. Default is 3 32-bit words. Maximum value is 32 32-
bit words.
Encoded PCI slave DTL read block size for memory read multiple
command
siz : read_block_siz
000:
001:
010:
011:
100: 128 bytes
101: 256 bytes
110: 512 bytes
111: 1024 bytes
Threshold for when DMA DTL requests more read data when initial
fetch is less than total dma length.
16 bytes
32 bytes
64 bytes
8 bytes
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 7: PCI-XIO Module
PNX15xx Series
7-30