PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 470

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 3:
Internal MBE state
fgpo_start
fgpo_stop
fgpo_data
clk_fgpo
Back-to-back Message Passing Example
XXXXX
2.8 Record or Message Counters
reached the FGPO from the memory, then D2 remains on the data bus until D3 is
available. Therefore extra samples are sent and could be detected by FGPI with an
OVERFLOW condition is the message has a know lenght.
The MBE condition is ‘sticky’ and can only be cleared by software writing a ‘1’ to the
FGPO_IR_CLR.MBE_ACK bit. However inside FGPO it is edge triggerred, i.e. if the
CPU clears the MBE interrupt while FGPO is still in MBE state the sticky bit is indeed
cleared and will not get set again unless FGPO gets out of the MBE state and comes
back to it. In the later case, yet another MBE interrupt will be generated.
Software must not disable FGPO upon and MBE occuring. It should let FGPO reach
the BUF{1,2}DONE state before disabling FGPO.
The registers FGPO_NREC1 and FGPO_NREC2 count the number of complete
records or messages output. The counters are incremented when a record or
message stop event is seen. The counters are cleared to zero when the associated
FGPO_BASEn register is updated.
Reading a FGPO_NRECn register while the associated buffer is active MAY NOT
RETURN THE ACTUAL TRANSFER COUNT (can be less than or equal to the actual
count) due to clock domain crossing logic. The best time to read a FGPO_NRECn
register is during the associated BUFnDONE interrupt service routine as the counter
is not updated during this time.
See
information on how to use FGPO_NRECn while the associated buffer is active.
Section 2.7.2 THRESH1_REACHED and THRESH2_REACHED Interrupts
D1
D2
Rev. 3 — 17 March 2006
Chapter 13: FGPO: Fast General Purpose Output
D3
D4
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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PNX15xx Series
D6
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for
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