PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 281

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 7:
1-bit shifted out
=> 32 samples
2-bit shifted out
=> 16 samples
4-bits shifted out
=> 8 samples
Up to 4-bit Samples per FIFO in Pattern Generation Mode
2.4 GPIO Error Behaviour
queue, 16 2-bit samples if 2 outputs are being driven by the FIFO queue or 8 4-bit
samples if 4 outputs are being driven by the FIFO queue. This is illustrated in
Figure
Remark: The number of samples to be generated is specified in a multiple of 32-bit
word being sent by the GPIO module. Therefore, there is no fine-grain way to specify
the exact amount of samples to be sent.
Additional GPIO Pattern Generation Feature: Timestamp Signal Generation
In pattern generation modes the GPIO can be programmed to generate events which
signal that the last 32-bit word read from a DMA buffer has arrived at a GPIO output
pin.
The event will be a positive edge pulse with the duration of the event to be greater
than or equal to 148 ns (2 x [1/13.5 MHz]). The specific event generated for each
FIFO queue is LAST_WORD.
LAST_WORD[3:0] have the same properties as the other internal signals as
described in
The generation of the LAST_WORD[3:0] internal signals is enabled by setting the
EN_EV_TSTAMP field of the relevant GPIO_EV[3:0] register.
A DMA buffer overrun, FIFO_OE, occurs if a new DMA buffer is not supplied by
software in time, i.e if BUF1_RDY and BUF2_RDY are both active.
Similarly to the software double DMA buffering scheme, the GPIO module also
implements a double internal buffering scheme per FIFO. This double buffering
scheme allows to hide the latency of the accesses to the system memory. Each
internal buffer is composed of an internal 64-byte memory. In sampling mode, the
GPIO uses one of the internal 64-byte memories to store the being sampled data
while the second 64-byte memory is being stored into memory. In pattern generation
mode, the 64-byte memories are used in the opposite direction. In both cases the
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IO_SEL_3 sample IO_SEL_2 sample IO_SEL_1 sample IO_SEL_0 sample
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Section 2.2
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Rev. 3 — 17 March 2006
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and listed in
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Chapter 8: General Purpose Input Output Pins
IO_SEL_1 sample IO_SEL_0 sample
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Section
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6
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4.15.
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IO_SEL_0 sample
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© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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