PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 198

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_SER_3
Product data sheet
Bit
2:1
0
Offset 0x04,740C
31:4
3
2:1
0
Offset 0x04,7410
31:4
3
2:1
0
Offset 0x04,7414
31:9
8
7
6
Symbol
sel_clk_gpio_q6_12_ctl
en_clk_gpio_q6_12_ctl
Reserved
turn_off_ack
sel_clk_gpio_13_ctl
en_clk_gpio_13_ctl
Reserved
turn_off_ack
sel_clk_gpio_14_ctl
en_clk_gpio_14_ctl
Reserved
turn_off_ack
Invert_fgpo_clock
fgpo_output_select
CLK_GPIO_13_CTL
CLK_GPIO_14_CTL
CLK_FGPO_CTL
Acces
s
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
…Continued
Value
00
1
-
0
00
1
-
0
00
1
-
0
0
0
Rev. 3 — 17 March 2006
Description
00: clk_gpio_q6_12_ctl = 27 MHz xtal_clk
01: clk_gpio_q6_12_ctl = DDS6
10: clk_gpio_q6_12_ctl = 27 MHz xtal_clk
11: clk_gpio_q6_12_ctl = LAN_TXD[3]
1: enable clk_gpio_q6_12_ctl
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_gpio_13_ctl = 27 MHz xtal_clk
01: clk_gpio_13_ctl = DDS5
10: clk_gpio_13_ctl = UNDEF
11: clk_gpio_13_ctl = LAN_RXD[0]
1: enable clk_gpio_13_ctl
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_gpio_14_ctl = 27 MHz xtal_clk
01: clk_gpio_14_ctl = DDS2
10: clk_gpio_14_ctl = UNDEF
11: clk_gpio_14_ctl = LAN_RXD[1]
1: enable clk_gpio_14_ctl
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
Invert FGPO clock
0 : do not invert the clock
1: invert the clock only to the fgpo block and not to the pad.
FGPO output select
0: Seperate output mode, The clock to the fgpo and to the pad
share the same source, but have seperate paths.
1: Feedback output mode, The clock is driven to the pad then is
feedback to the clock block. It then goes through gating logic to the
fgpo block.
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
5-47