PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 540

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
3.12 Software Reset
Upon receipt of an ACK, the AI hardware removes the related interrupt request line
assertion at the next CPU clock edge. The AI interrupt should always be operated in
level-sensitive mode since AI can signal multiple conditions that each need
independent ACKs over the single internal SOURCE 11 request line.
In normal operation, the CPU and AI hardware continuously exchange buffers without
ever losing a sample. If the CPU fails to provide a new buffer in time, the OVERRUN
error flag is raised. The flag is not affected by ACK1 or ACK2; it can only be cleared
by an explicit ACK-OVR.
Bit 31 of the AI_CTL register is the software reset bit for the Audio Input module.
The purpose of SW reset register bit is to cleanly abort DMA traffic, reset the Audio
Input logic and reset all MMIO registers. SW reset must not hang the MMIO bus
interface (i.e. MMIO bus state machine is not reset).
Although the IP clock should be running (i.e. not gated off to save power) when the
SW reset bit is written, the system will not hang if a SW reset is executed when the
clocks are off (this means in master mode that the clock needs to be switched to the
27 MHz crystal clock since SER_MASTER is also reset and therefore the clock is
removed.
Remark: that SW reset makes no attempt to stop DMA data transfer in a precise
manner.
The following sequence takes place following a software reset:
1. CPU sets the SW reset bit via an MMIO interface write and then polls that bit
2. Although this MMIO interface write completes immediately, accesses to all other
3. The SW reset handshake is asserted to indicate that the above actions in both
waiting for it to be cleared indicating reset completion.
registers are disabled until a round trip handshake with the Audio Input clock
domain indicates that all SW reset action is complete. If a read to a register other
than the SW reset register occurs while the interface is disabled then the error
condition and 0xDEADABA data are immediately returned. If a read to the SW
reset register occurs then a 1 is returned immediately with no error condition to
indicate that the SW reset is still in progress. A toggle style handshake between
the bus and Audio Input clock domains is already built into the new MMIO
interface register for SW reset. The Audio Input completes the following actions
before the handshake completion signal is asserted:
clock domains are complete. This causes the SW reset bit to be de-asserted and
the MMIO interface to be enabled.
a) Disable the streaming interface
b) Abort DMA
c) Reset IP logic
d) Reset MMIO registers in both Audio Input and bus clock domains
Rev. 3 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 16: Audio Input
16-14