PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 124

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
6.3 System Parameters for TM3260
Few more control parameters are available to tune the use of TM3260 and PNX15xx
Series. The MMIO register layout and offsets are described in
Remark: It is not recommended to have the TM3260 to flip itself to ‘1’ the
TM32_PWRDWN_REQ bit.
•
•
•
The CPU apertures (DRAM and APERT1 described in
modified by the TM3260 itself, if the TM32_APERT_MODIFIABLE bit is set to ‘1’.
In host mode the host CPU can decide to prevent TM3260 to go out of its allowed
apertures by flipping to ‘0’ the bit TM32_APERT_MODIFIABLE.
The TM32_LS_DBLLINE and TM32_IFU_DBLLINE parameters influence the
overall performance of the TM3260. These parameters are related to the cache
line sizes and the optimal memory burst than can be obtained with PNX15xx
Series MMI. The default values favor the main memory bandwidth usage and
improve, in most cases, the TM3260 processing power. However some
applications may require a shorter memory burst to reduce the bandwidth usage
or to avoid some pathological cache trashing cases. TM32_LS_DBLLINE and
TM32_IFU_DBLLINE can then be flipped to ‘0’. There is no available formula to
know if a particular application benefits from one setting or the other.
Experimentation on the final application is recommended to determine the
optimal settings.
It is possible for a host CPU to shutdown entirely the high speed clock of the
TM3260. The safe procedure consists in first requesting the TM3260 to prepare
itself for major powerdown mode. The host CPU needs first to alert the software
running on the TM3260 that a powerdown sequence is coming. The TM3260
software acknowledges that it is ready. Then the host CPU toggles the
TM32_PWRDWN_REQ bit to inform the TM3260 module that a full powerdown
mode is requested. The TM3260 hardware state machine replies by asserting the
TM32_PWRDWN_ACK bit. From this point TM3260 will not answer to any
request and its high speed CPU clock can be turned off by the CPU host. The
wake-up sequence starts by turning back on the high speed CPU clock and then
flip to ‘0’ the TM32_PWRDWN_REQ bit.
Rev. 3 — 17 March 2006
Chapter 3: System On Chip Resources
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Section
Section
2.2) can be
6.3.1.
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