PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 152

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

1. Introduction
2. Functional Description
The Clock module is the heart of the PNX15xx Series system. Its role is to provide
and control all the clocks of the system. The main characteristics of the Clock module
is to be low cost. It generates all the PNX15xx Series system clocks from one unique
source, a 27 MHz input crystal. The clock module features can be regrouped as
follows:
The Clock Module has three main internal interfaces:
A 27 MHz crystal clock provides the source clock for all PLLs in the CAB block and for
the low jitter PLL. The PLLs are programmable from the Clock module registers to
generate a range of possible frequencies. The DDS blocks are required to make
slight adjustments to each video and audio clock to track transmission sources.
Software controls this tracking by programming the relevant DDS block to adjust the
clock. These adjustments are made in steps of 0.4 Hz. The DDS clocks are derived
from the internal 1.728 GHz PLL (64 times the 27 MHz input crystal). The DDS jitter
is less than 0.58 ns. The video clock requirements may require a shorter term jitter so
an additional PLL is provided to smooth out the DDS jitter. This combines the two
video clock requirements, low jitter and high precision adjustment of the clock
frequency to meet color burst requirements but also track the audio signals.
The Clock Module consists of an MMIO-interface with programmable Clock and PLL
control registers, and a series of control logic for every clock generated. The clock
control logic will consist of:
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Chapter 5: The Clock Module
PNX15xx Series Data Book – Volume 1 of 1
Rev. 3 — 17 March 2006
Use of Phase Locked Loop (PLL) circuits, Direct Digital Synthesizers (DDS) or
simple clock dividers to meet the frequency and jitter requirements of all
PNX15xx Series modules.
All the clocks are software programmable and support powerdown features.
Clock switching or clock frequency changes occur glitch free thank to dedicated
hardware.
an interface to a Custom Analog Block (CAB). The CAB module includes 2 PLLs,
several high speed clock dividers and 9 DDS blocks.
an interface to a dedicated low jitter PLL used for the DDR memory controller.
an MMIO interface to allow the programming of all configuration registers.
Product data sheet