PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 214

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 7: Flash TIming Parameters Used by the Default Boot Scripts
PNX15XX_SER_3
Product data sheet
Parameter
MISC_CTRL
SEL0_16BIT
SEL0_USE_ACK
SEL0_WE_HI
SEL0_WE_LO
SEL0_WAIT
SEL0_OFFSET
SEL0_TYPE
SEL0_SIZ
EN_SEL0
SINGLE_DATA_PHASE
SND2XIO
FIX_ADDR
MAX_BURST_SIZE
INIT_DMA
CMD_TYPE
NOR Flash
Bit Field Value
0
BOOT_MODE[2]
pin
0
0
0
6
0
1
0
1
0
1
0
4
1
6
The next Section 3.3.1.1 contains the content, in hexadecimal, of the Flash boot
scripts.
3. The boot module executes an idle loop to wait for the completion of the fetched
4. The last step before completing the terminate boot command is to set up the
register and the DMA Controls MMIO register are the two MMIO registers
modified by the boot script. The remaining MMIO registers use the reset state of
the PCI module.
data from the Flash memory device to the main memory.
TM3260 DRAM aperture registers and kick off the TM3260 CPU.
Comment
Fixed wait states
N/A
N/A
6 PCI clock cycles for the
Output Enable signal
No Offset
NOR Flash
8 Megabytes
Enabled
Target XIO
Linear address
128 data phases
Start to fetch data
XIO read command
Rev. 3 — 17 March 2006
NAND Flash
Bit Field Value
0
BOOT_MODE[2]
pin
1
0xA
0xA
2
0
2
0
1
0
1
0
4
1
6
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 6: Boot Module
Comment
Wait for ack
10 PCI clock cycles of
HIGH and LOW time for
REN
10 PCI clock cycles of
HIGH and LOW time for
REN
2 PCI clock cycles for the
address to data phase
delay
No Offset
NAND Flash
8 Megabytes
Enabled
Target XIO
Linear address
128 data phases
Start to fetch data
XIO read command
6-11