PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 817

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

1. Introduction
2. Functional Description
The PNX15xx Series Device Control and Status (DCS) Network architecture is
designed to support the following:
The DCS bus is intended for MMIO traffic to configure the various modules in the
system. All modules can be accessed by the Boot module, and external PCI master
or the TM3260 itself. Access between the DCS bus and the memory is provided by
the DCS-Gate. This path is to be used by the boot module only!
page 3-30
bus.
A generic “Device Transaction Level” (DTL) point-to-point initiator-target
communication protocol is used on the boundary between a module and the DCS
bus. MMIO communication through the DTL protocol always consists of a single 32-
bit data element.
Each module on the DCS bus has a unique ID. The bus controller provides
programmable timeout generation with the following features:
The DCS network controllers generate selects for all the DCS targets according to
the address on the DCS network aperture map. See
Resources,
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Chapter 30: DCS Network
PNX15xx Series Data Book – Volume 1 of 1
Rev. 3 — 17 March 2006
Separates MMIO traffic from DMA traffic:
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Provides low latency access to modules:
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Supports timeout generation.
Captures error and timeout information:
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Allows interrupt generation for any non-masked timeouts and errors.
The TM3260 core has a high-performance, low-latency path to memory.
TM3260 ICache and DCache traffic is separated.
The TM3260 core has a low latency access to different modules of PNX15xx
Series system.
Initiator ID of the currently granted DCS Initiator
32-bit address of the currently granted DCS transaction
Encoded Target number for the currently selected DCS device
Additional information including read or write command information
in
Section 11. on page 3-31
Chapter 3 System On Chip Resources
for addresses of DCS target apertures.
pictures PNX15xx Series DCS
Chapter 3 System On Chip
Product data sheet
Figure 3 on