PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 123

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 5: Interrupt Source Assignments
PNX15XX_SER_3
Product data sheet
SOURCE NAME
DCS
MMI
Reserved
6.2 Timers
SOURCE
NUMBER
60
61
62...63
The TM3260 CPU contains four programmable timer/counters, all with the same
function. The first three (TIMER1, TIMER2, TIMER3) are intended for general use.
The fourth timer/counter (SYSTIMER) is reserved for use by the system software and
should not be used by applications.
Each timer/counter can be set to count one of the event types specified in
Note that source 3 to 6 are special TM3260 events used for program debug support
as well as cache performance monitoring. Full description can be found in [1]. For all
the other source signals, like the VDO_CLK1 pin, positive-going edges on the signal
are counted. Each timer increments its value until the programmed count is reached.
On the clock cycle when the timer reaches its programmed count value, an interrupt
is generated.
The timer interrupt source mode should be set as edge-sensitive as presented in
Table
Table 6: TM3260 Timer Source Selection
SOURCE NAME
TM3260 CLOCK
PRESCALE
Reserved
DATABREAK
INSTBREAK
CACHE1
CACHE2
VDI_CLK1
VDI_CLK2
VDO_CLK1
VDO_CLK2
AI_WS
AO_WS
GPIO_TIMER0
GPIO_TIMER1
REFERENCE_CLOCK
5. No software interrupt acknowledge to the timer device is necessary.
INTERRUPT
OPERATING MODE
level
level
n/a
Rev. 3 — 17 March 2006
SOURCE NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SOURCE DESCRIPTION
Internal DCS bus
Main Memory Interface, i.e. the DRAM controller
Reserved for future devices
Chapter 3: System On Chip Resources
SOURCE DESCRIPTION
The CPU clock
Pre-scaled CPU clock
Reserved for future devices
Data breakpoints
Instruction breakpoints
Cache event 1
Cache event 2
VIP clock pin
FGPI clock pin
QVCP clock pin
FGPO clock pin
AI Word Strobe pin
AO Word Strobe pin
GPIO pin selection 0
GPIO pin selection 1
The 27 MHz input crystal clock
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Table
6.
3-14