PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 403

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 20: QVCP 1 Registers
PNX15XX_SER_3
Product data sheet
Bit
27:16
15:12
11:0
Offset 0x10 E030
31:28
27:0
Offset 0x10 E034
31:1
0
Offset 0x10 E038
31:12
11:0
Offset 0x10 E03C
31:25
24
23
22
21
20:19
18
17:16
15
14:13
Symbol
INT_START_E
Unused
INT_START_O
Unused
VBI_SRC_ADDR
Unused
VBI_EN
Unused
VBI_SENT_OFFSET
Unused
TC_outS1R/Y
TC_outS1G/U
TC_outS1B/V
DNS1
Unused
Qualifier
Outmode
parallel_mode
Unused
VBI SRC Address
VBI_CTRL
VBI_SENT_OFFSET
OUT_CTRL
…Continued
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
-
0
-
0
-
0
-
0
-
1
1
1
0
-
0
0
0
-
Value
Rev. 3 — 17 March 2006
Description
Horizontal offset for VSYNC start even field (interlaced mode only)
Vsync appears at INT_START_E + 1.
Horizontal offset for VSYNC start odd field (interlaced mode only)
Vsync appears at INT_START_O + 1.
VBI data source address
Enable VBI data fetch engine.
This programming value specifies the number of lines to add to the
linecnt value in the packet identifier.
Set to unsigned format for the Y/R channel of the D1 slice:
Set to unsigned format for the U/G channel of the D1 slice:
Set to unsigned format for the V/B channel of the D1 slice:
444:422 down sample enable
1 = slice qualifier is put out
0 = hsync is put out
00 = output interface runs is d1 mode
01 = output interface runs in double-d1 mode
10 = output interface operates in up to 30 bit parallel mode
11 = unused
This bit controls the sync delay compensation.
1 = syncs are delayed (needed for 24-bit parallel output mode)
0 = no additional sync delay
1 = invert the MSB of the Y/R channel for the D1 slice
0 = leave D1 slice untouched
1 = invert the MSB of the U/G channel for D1 slice
0 = leave D1 slice untouched
1 = invert the MSB of the V/B channel for D1 slice
0 = leave D1 slice untouched
1 = down sample filter enabled
0 = down sample filter bypassed
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 11: QVCP
11-50