PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 652

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 1: Software Reset Procedure
PNX15XX_SER_3
Product data sheet
Cycle No.
i
i to j
k
Action
The CPU issues the ‘Reset the Variable Length Decoder’
command by writing the corresponding command code
into the VLD_COMMAND register.’
The VLD will complete any DMA transactions that are
already in progress. Any new DMA transactions will be
aborted. The VLD then raises the vld_ready_to_reset
signal.
If (vld_ready_to_reset) then the VLD interrupts the CPU. Assumes k>j; otherwise it is jth cycle. The full reset
3.2.1 VLD Status (VLD_MC_STATUS)
3.2 VLD MMIO Registers
progress will be aborted.
The “Reset the Variable Length Decoder” command
Soft Reset is controlled by the hardware so that any DMA activity that is in progress
will complete before the soft reset has a complete effect. Software should wait for the
“VLD Command Done” status bit to be set before proceeding with the next command.
Remark: The VLD_INP_CNT is cleared after reset. However, this is not treated as a
DMA_INPUT_DONE condition in the VLD and the CPU will not be interrupted by the
VLD after reset with a DMA_INPUT_DONE condition. The MPEG video bitstream
buffer should be refilled as needed and the VLD_INP_CNT rewritten with a proper
value before issuing new commands to the VLD after reset.
The VLD_MC_STATUS register contains current status information which is most
pertinent to the normal operation of an MPEG video decode application. Writing a
logic ‘1’ to any of the status bits other than bit-0 clears the corresponding bit. Writing
a logic ‘0’ has no effect. Exception: Bit 0 (Command Done) is cleared only by issuing
a new command. Writing a logic ‘1’ to bit zero of the status register will result in
undefined behavior of the VLD . Note that several status bits may be asserted
simultaneously.
Table 2
lists the function of each status field.
Rev. 3 — 17 March 2006
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
Remarks
Any DMA transactions, once started, will not be
aborted in the middle.
clears all internal buffers, state machines, and
leaves the following registers with the value of 0x0:
VLD_COMMAND
VLD_CTL
VLD_BIT_CNT
VLD_INP_CNT
VLD_MBH_CNT
VLD_RL_CNT
The VLD_STATUS register contains the value
0x0000_0001.
Section 3.2.9 on page 21-7
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
or
21-4