PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 515

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 4:
SCK
WS
SDx
Serial Frame (64 Bits) of a 18-Bit Precision I
0
2.6.1 Serial Frame Limitations
2.6.2 WS Characteristics
2.6.3 I
1
left channel data
2
3
Due to the implementation, there is a minimum serial frame length requirement that is
operating-mode dependent according to
Table 4: Minimum Serial Frame Length in Bits
The WS signal is used to define the start point of a serial frame. The start of a frame
can be marked by a transition on WS 1 clock before the start of the first bit of a new
frame. This WS transition can be programmed to be either a positive or a negative
edge transition.
In addition, the WS signal can be programmed to be a 50% duty cycle wave form or a
pulse that is 1 clock cycle wide. If the WS is configured to be 1 single clock wide
pulse, the pulse spans the 2 clock cycles preceding the first bit of the new frame. If
the WS is configured to be a 50% duty cycle waveform, the active edge of the WS
signal occurs 1 clock cycle before the first bit of the new frame. If the serial frame is of
an even bit count, then the second transition of the WS signal occurs in the clock
cycle before the halfway point of the serial frame. If the serial frame is of an odd bit
count, then the portion of the WS wave that is in the low state has the extra clock
cycle.
With an odd bit count for a serial frame and with a frame starting with a negative edge
of the WS, a 50% duty cycle WS signal would have the first part of the WS signal 1
clock longer than the second half. With a positive edge of the WS signal marking the
start of a serial frame, the second half of the serial frame would have a WS signal
longer by 1 clock cycle.
Figure 4
to transmit 16 or 32 bits of stereo data via an I
converter with a 64-bit serial frame.
Operating Mode
16 bit/sample, mono
32 bit/sample, mono
16 bit/sample, stereo
32 bit/sample, stereo
2
S Serial Framing Example
n (
and
17 18
18)
Table 5
30 31 32 33
Rev. 3 — 17 March 2006
show how the Audio Out module MMIO registers should be set
right channel data
2
S D/A Converter
13 bits
13 bits
13 bits
36 bits
Minimum Serial Frame Length
49 50 51
n
Table
(18)
2
4.
52
S serial standard to an 18-bit D/A
62 63
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 15: Audio Output
0
left channel data
1
n+1
(18)
15-8