PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 574

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 6: SPDIF Input Registers
PNX15XX_SER_3
Product data sheet
Bit
2
1
0
Offset 0x10 A004
31:6
5:0
Offset 0x10 A008
31:6
5:0
Offset 0x10 A00C
31:6
5:0
Offset 0x10 A010
31:0
Offset 0x10 A014
31:8
Symbol
DIAG_MODE
CAP_ENABLE
RESET
BASE1
Reserved
BASE2
Reserved
SIZE (in bytes)
Reserved
ADDRESS
Unused
SPDI_BASE1
SPDI_BASE2
SPDI_SIZE
SPDI_BPTR
SPDI_SMPMASK
…Continued
Acces
s
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R
R
Value
0
0
0
0
0
0
0
0
0
0
-
Rev. 3 — 17 March 2006
Description
Diagnostic loopback mode. Used to diagnose the SPDIF Input
module.
Writing a ‘1’ to this bit enables capture per the selected mode.
Writing a ’0’ here stops any ongoing capture after completing any
actions related to the current audio sample.
Writing a ‘1’ to this bit resets the SPDI block. The registers of the
SPDI will all be reset to ‘0s’. This should be used with caution. Any
ongoing capture will be interrupted.
Selects the main memory buffer starting addresses used for DMA of
audio data samples.
Note: Any change to the SPDI_BASE1 register should only be done
while a memory buffer is not being used by the hardware DMA.
If changed it must be set before BUF1_FULL_CLR.
Selects the main memory buffer starting addresses used for DMA of
audio data samples.
Note: Any change to the SPDI_BASE2 register should only be done
while a memory buffer is not being used by the hardware DMA.
If changed it must be set before BUF2_FULL_CLR.
Hardwired to logic ‘0’
The size of the DMA buffers is specified in the SPDI_SIZE register.
Note hardware limits the buffer size and starting address to be
aligned to 64-byte addresses. Assignment to SPDI_BASE1,
SPDI_BASE2 and SPDI_SIZE have no effect on the state of the
SPDI_STATUS flags.
Hardwired to logic ‘0’
To aid software with finding the start of a block in memory, the
SPDI_BPTR contains the address of the first occurrence of a frame
0 (indicating the starting boundary of a complete 192-frame block)
within the currently filling memory buffer: BUF1 or BUF2. This is
useful during capture of non-PCM coded data found in IEC61937
data streams.
0 = The SPDIF input source is set to the SPDIF Input input pin
(default).
1 = The SPDIF input source is set to the SPDIF OUT pin.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 18: SPDIF Input
18-18