PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 664

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 9:
Table 10: VLD Registers
PNX15XX_SER_3
Product data sheet
Offset
0x07 501C
0x07 5020
0x07 5024
0x07 5028
0x07 502C
0x07 5030
0x07 5034
0x07 5200
0x07 5FF4
0x07 5FFC
Bit
Offset 0x07 5000
31:12
11:8
7:0
Offset 0x07 5004
31:15
15:0
Offset 0x07 5008
31:5
4:0
Offset 0x07 500C
Symbol
Reserved
Command
Mblock/Shift Count or
start code
Reserved
Shift Register
Reserved
Quant scale
Register Summary
Symbol
VLD_INP_ADR
VLD_INP_CNT
VLD_MBH_ADR
VLD_MBH_CNT
VLD_RL_ADR
VLD_RL_CNT
VLD_BIT_CNT
MC_PICINFO0
PD
MODULE ID
5.3 Register Table
VLD_COMMAND
VLD_SR
VLD_QS
VLD_PI
…Continued
Acces
s
R
R/W
R/W
R
R
R
R/W
0
0
NI
NI
Value
Description
VLD Input Memory Address
VLD Input Count gives the number of bytes to be read from main memory
VLD Macroblock Header Writeback Address
VLD Macroblock Header Writeback Count
VLD Run-level Writeback Address
VLD Run-level Writeback Count
VLD Bit Count gives the number of bits consumed by the VLD
Macro-block height
Power Down Register
Module Identification Register
Rev. 3 — 17 March 2006
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
Description
Command code of the VLD command to be executed
0x1 = Shift Bitstream by “Shift Count” bits
0x2 = Parse Macroblock
0x3 = Search for next Start Code
0x4 = Reset Variable Length Decoder
0x5 = Initialize VLD
0x6 = Search for the Start Code given in bits [7:0].
0x7 = Parse Macroblock Row
0x8 = Flush Write FIFOs
0x9 = Parse Long
For the ‘Shift Bitstream’ command, only the lower 4-bit are used; the
upper 4-bit should be set to 0. All 8 bits are used for the ‘Parse
macroblocks’ and ‘Search for given start code’ commands. For
Parse Long command these bits cannot be programmed to 0.
This register is a shadow of the VLD’s operational shift register and
it allows the DSPCPU to access the bitstream through the VLD. Bits
15 through 0 are the current contents of the VLD shift register.
This register contains the quantization scale code to be output by
the VLD until it is overridden by a macroblock quantizer scale code.
The quantizer scale code is part of the macroblock header output.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
21-16