PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 340

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 9: Register Description
PNX15XX_SER_3
Product data sheet
Bit
12:0
Offset 0x06 5084
31:13
12:0
Offset 0x06 5088
31:4
3:0
Offset 0x06 50C0
31:4
3:0
Offset 0x06 50C4
31:4
3:0
Offset 0x06 50D0
31:4
Symbol
MR
Unused
EMR
Unused
PRECHARGE_BIT
Unused
ROW_WIDTH
Unused
COLUMN_WIDTH
Unused
DDR_EMR
DDR_PRECHARGE_BIT
RANK0_ROW_WIDTH
RANK0_COLUMN_WIDTH
RANK1_ROW_WIDTH
Access Value
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
0x043
-
0x000
-
0xa
-
0xd
-
0xa
-
Rev. 3 — 17 March 2006
Description
Mode register. The assumption is the DLL reset bit is at location 8.
Use the datasheet of the DDR memory to determine the value of
this register. The reset value of this register represents a CAS
latency of 3.0 cycles, and a burst length of 8. Make sure to select a
burst size of 8, and a sequential burst type to ensure correct
IP_2031 operation.
The following is taken from a DDR datasheet and describes the
different bits of the mode register.
Bits 0 up to 2: burst length
Bit 3: burst type (‘0’: sequential, ‘1’: interleaved)
Bits 4 up to 6: CAS latency
Bits 7 and up: operating mode (‘0’: normal operation, ‘2’: normal
operation/reset DLL)
These bits should be ignored when read, and written as 0s.
Extended Mode Register. Use the datasheet of the DDR memory to
determine the value of this register.
For emulation purposes it may be required to disable the DLL. To
this end, make sure that bit 0 of this register contains a ‘1’. In normal
(non-emulation) mode, make sure that bit 0 of this register contains
a ‘0’.
The following is taken from a DDR datasheet and describes the
different bits of the extended mode register.
Bit 0: DLL (‘0’: enable, ‘1’: disable).
Bit 1: drive strength (‘0’: normal, ‘1’: reduced)
Bit 2: QFC mode
Bits 3 and up: operating mode
These bits should be ignored when read, and written as 0s.
Column bit responsible for precharge. Only the values 0x8 (bit 8)
and 0xa (bit 10) are supported.
These bits should be ignored when read, and written as 0s.
Row dimension: 2^ROW_WIDTH rows i.e., a value of 0xC specifies
2^12 = 4096 rows. Only the following values are supported:
0x8, 0x9, 0xa, 0xb, 0xc, and 0xd (supporting 256 up to 8192 rows).
These bits should be ignored when read, and written as 0s.
Column dimension: 2^COLUMN_WIDTH columns (each column
has a width of 32 bit). I.e., a value of 0xa specifies 2^10 = 1024
columns of 32 bit each. Only the following values are supported:
0x8, 0x9, 0xa, and 0xb (supporting 256 up to 2048 columns).
These bits should be ignored when read, and written as 0s.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Chapter 9: DDR Controller
PNX15xx Series
9-27