PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 166

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
2.5 Power-up and Reset sequence
2.6 Clock Stretching
Table 8: Bypass Clock Sources
On power-up, the Clock module outputs the default 27 MHz clocks to all the PNX15xx
Series modules. Once the Reset module has released the internal module resets, the
boot-up sequence executed by the Boot module starts off the 27 MHz clock. At some
point in the boot up sequence, the Boot module switches TM3260 and the DDR
clocks to the associated PLLs, PLL0 and PLL2. The Clock module keeps feeding the
other PNX15xx Series modules with the initial 27 MHz clock until the software
decides otherwise.
The TM3260 clock, clk_tm, can be paused or stretched for one clock pulse. A counter
counts to a pre-programmed value. When this value is reached the clock gating circuit
will turn off the TM3260 clock for one clock period. Then the TM3260 clock is turned
back on.
The procedure to operate the clock stretching circuit is to program the
CLK_STRETCHER_CTL MMIO register to the value desired between clock
stretches. For example a value of 3 turns off the clock every 3 clocks as pictured in
Figure
A Write to the CLK_STRETCHER_CTL register acts as the enable for the feature.
Clocks from Clock
Module
clk_qvcp
clk_qvcp_pix
clk_qvcp_proc
clk_lcd_tstamp
clk_vip
clk_vld
ai_osclk
ao_osclk
clk_spdo
clk_spdi
clk_gpio_q4
clk_gpio_q5
clk_gpio_q6_12
clk_gpio_13
clk_gpio_14
clk_fgpo
clk_fgpi
5.
Rev. 3 — 17 March 2006
Bypass Control Register
CLK_QVCP_OUT_CTL
CLK_QVCP_PIX_CTL
CLK_QVCP_PROC_CTL
CLK_LCD_TSTAMP_CTL
CLK_VIP_CTL
CLK_VLD_CTL
AI_OSCLK_CTL
AO_OSCLK_CTL
CLK_SPDO_CTL
CLK_SPDI_CTL
CLK_GPIO_Q4_CTL
CLK_GPIO_Q5_CTL
CLK_GPIO_Q6_12_CTL
CLK_GPIO_13_CTL
CLK_GPIO_14_CTL
CLK_FGPO_CTL
CLK_FGPI_CTL
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
GPIO pin
Assignment
XIO_ACK
XIO_D[8]
XIO_D[9]
XIO_D[10]
XIO_D[11]
XIO_D[12]
XIO_D[13]
XIO_D[14]
XIO_D[15]
LAN_TXD[0]
LAN_TXD[1]
LAN_TXD[2]
LAN_TXD[3]
LAN_RXD[0]
LAN_RXD[1]
LAN_RXD[2]
LAN_RXD[3]
5-15