PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 193

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_SER_3
Product data sheet
Bit
5
4
3
2:1
0
Offset 0x04,7204
31:7
6
5:3
2:1
Symbol
Invert_qvcp_clock
qvcp_output_select
qvcp_output_enable_n
sel_clk_qvcp
en_clk_qvcp
Reserved
turn_off_ack
div_clk_qvcp_pix
sel_clk_qvcp_pix
CLK_QVCP_PIX_CTL
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
…Continued
Value
0
0
1
00
1
-
0
001
00
Rev. 3 — 17 March 2006
Description
Invert QVCP clock
0 : do not invert the clock
1: invert the clock only to the qvcp block and not to the pad.
QVCP output select
0: Seperate output mode, The clock to the qvcp and to the pad
share the same source, but have seperate paths. This mode is also
the LCD only mode (see QVCP/LCD description). If the LCD only bit
is set then this bit cannot be set to a ‘1’ (feedback mode).
1: Feedback output mode, The clock is driven to the pad then is
feedback to the clock block. It then goes through gating logic to the
qvcp block.
QVCP output enable
0: output, the clock is generated internally
1: input, the clock is provided by an external source. Note: during
and after reset the xtal clock is forced onto the qvcp clock. In order
to actually allow the input clock to go to the qvcp this register must
be written to. This also implies that writing qvcp_output_enable_n =
1 overrides a sel_clk_qvcp = 0.
The following 3 settings are valid when qvcp_output_enable_n = 0.
00: clk_qvcp = 27 MHz xtal_clk (see qvcp_output_enable_n).
01: clk_qvcp = PLL1
10: clk_qvcp = PLL1
11: clk_qvcp = XIO_ACK
The following setting is valid when qvcp_output_enable_n = 1 (The
input mode).
01: clk_qvcp_out = VDO_CLK1
1: enable clk_qvcp
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
000: clk_qvcp_pix_src = qvcp_clk_out clock divided by 1
001: clk_qvcp_pix_src = qvcp_clk_out clock divided by 2
010: clk_qvcp_pix_src = qvcp_clk_out clock divided by 3
011: clk_qvcp_pix_src = qvcp_clk_out clock divided by 4
100: clk_qvcp_pix_src = qvcp_clk_out clock divided by 6
101: clk_qvcp_pix_src = qvcp_clk_out clock divided by 8
(refer to
00: clk_qvcp_pix = 27 MHz xtal_clk
01: clk_qvcp_pix = clk_qvcp_pix_src
10: clk_qvcp_pix = clk_qvcp_pix_src
11: clk_qvcp_pix = XIO_D[8]
Figure 17
for the qvcp_clk_out)
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
5-42