PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 191

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_SER_3
Product data sheet
Bit
2:1
0
Offset 0x04,711C
31:4
3
2:1
0
Offset 0x04,7120
31:4
3
2:1
0
Offset 0x04,7124
31:4
3
2:1
0
Offset 0x04,7128
31:7
Symbol
sel_clk_lan
en_clk_lan
Reserved
turn_off_ack
sel_clk_lan_rx
en_clk_lan_rx
Reserved
turn_off_ack
sel_clk_lan_tx
en_clk_lan_tx
Reserved
turn_off_ack
sel_clk_iic
en_clk_iic
Reserved
CLK_LAN_RX_CTL
CLK_LAN_TX_CTL
CLK_IIC_CTL
CLK_DVDD_CTL
Acces
s
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R
R/W
R/W
R/W
…Continued
Value
00
1
-
0
00
1
-
0
00
1
-
0
00
1
-
Rev. 3 — 17 March 2006
Description
00: clk_lan = 27 MHz xtal_clk
01: clk_lan = clk_lan_src
10: clk_lan = 27 MHz xtal_clk
11: clk_lan = AO_SD[0]
1: enable clk_lan
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_lan_rx = 27 MHz xtal_clk
01: clk_lan_rx = CLK_LAN_RX pin
10: clk_lan_rx = 27 MHz xtal_clk
11: clk_lan_rx = CLK_LAN_RX pin
1: enable clk_lan_rx
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_lan_tx = 27 MHz xtal_clk
01: clk_lan_tx = CLK_LAN_TX pin
10: clk_lan_tx = 27 MHz xtal_clk)
11: clk_lan_tx = CLK_LAN_TX pin
1: enable clk_lan_tx
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
0 - Indicates if the enabled clock is running
1 - Indicates that the clock is being blocked during a frequency
change to avoid glitches
00: clk_iic_tx = 27 MHz xtal_clk
01: clk_iic_tx = clk_24
10: clk_iic_tx = 27 MHz xtal_clk
11: clk_iic_tx = AO_SD[1]
1: enable clk_iic
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Chapter 5: The Clock Module
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
5-40