PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 437

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 5: Field Identifier Generation Modes
PNX15XX_SER_3
Product data sheet
VDI8
x
f
x
x
* FID toggles after detection of video window start.
Figure 10: Field Identifier Timing
HREF
f
x
x
x
FID
FID
FID
HREF
VREF
VSEL
VMI
D1
x
x
ZERO
TGL
VMI
FZERO
0
0
1
x
value takes effect after the selected vertical reference edge occurs at the input. The
SF bit controls how the Field Identifier value is interpreted. Any change of the Field
Identifier interpretation takes effect immediately.
Video Acquisition Window
The start location of the window to be captured, relative to the input stream, is
specified in the Window Start registers, 00140 ( VID_XWS, VID_YWS ).
The stop location of the window to be captured, relative to the input stream, is
specified in the Window End register, 00144 ( VID_XWE, VID_YWE ).
Additional Target window cropping, which might be necessary after scaling, can be
done with the LINE_SIZE and LINE_COUNT values in the Target Window Size
register, 00304.
Dithering of the Video Data
There are two identical Dither units, Pre-Dither and Post-Dither, capable of 10->9, 10-
>8 and 9->8 dithering/rounding with saturating values. These two dither units are
cascaded together on the video data path. The two dither units are independent of
each other, and controlled with separate MMIO registers. Input samples are assumed
to be left (MSB) aligned on the 10 bit input bus. Output samples are left aligned
(MSB) on the 10 bit output bus. Both Dither units need to be disabled for an 8-bit input
data stream, to avoid unexpected results.
FTGL & FZERO bits
change of
falling edge
FTGL
0
0
0
1
of VREF
Change at
negedge VREF
valid D1 Header
immediately
immediately*
Rev. 3 — 17 March 2006
VID
start of video
_
VID
window
YWS
_
XWS
FID
!f
f
0
0,1,0,..
falling edge
of VREF
Chapter 12: Video Input Processor
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
start of video
FID
0
1
0
1
window
FSWP
0
0
1
1
Meaning
Odd
Even
Even
Odd
12-10