PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 32

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
Table 4: PNX1500 Interface
PNX15XX_SER_3
Product data sheet
Pin Name
MM_CLK
MM_CLK_N
MM_CS1_N
MM_CS0_N
MM_RAS_N
MM_CAS_N
MM_WE_N
MM_CKE
AVREF
MM_BA1
MM_BA0
MM_ADDR12
MM_ADDR11
MM_ADDR10
MM_ADDR09
MM_ADDR08
MM_ADDR07
MM_ADDR06
MM_ADDR05
MM_ADDR04
MM_ADDR03
MM_ADDR02
MM_ADDR01
MM_ADDR00
MM_DQM3
MM_DQM2
MM_DQM1
MM_DQM0
MM_DQS3
MM_DQS2
MM_DQS1
MM_DQS0
BGA
Ball
M1
M2
M4
G1
V4
N3
N2
P4
R4
K4
K3
N4
P1
R1
U3
U4
P3
R2
U2
V3
K2
V1
Y1
L3
L1
J2
T4
L4
T1
T3
J4
J1
Pad
Type
SSTLREFGEN
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLADDIO
SSTLCLKIO
SSTLCLKIO
SSTLDATIO
SSTLDATIO
SSTLDATIO
SSTLDATIO
Rev. 3 — 17 March 2006
I/O
Type
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
I/O
I/O
I/O
IN
GPIO
#
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
P Description
-
-
-
-
- Row address strobe. It is active low.
- Column address strobe. It is active low.
- Write enable. It is active low
- Clock enable output to DDR SDRAMs.
- Voltage reference.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DDR SDRAM Output Clock. Refer to
on page 1-51
Chip select for DDR SDRAM. It is active low.
DDR SDRAM bank address. It supports 4-bank
types of SDRAMs.
DDR SDRAM address bus. It is used for row and
column addresses.
Byte write enable signals:
MM_DQM0 is attached to byte MM_DATA[7:0]
MM_DQM1 is attached to byte MM_DATA[15:8]
MM_DQM2 is attached to byte MM_DATA[23:16]
MM_DQM3 is attached to byte MM_DATA[31:24]
Byte strobe signals:
MM_DQS0 is attached to byte MM_DATA[7:0]
MM_DQS1 is attached to byte MM_DATA[15:8]
MM_DQS2 is attached to byte MM_DATA[23:16]
MM_DQS3 is attached to byte MM_DATA[31:24]
Chapter 1: Integrated Circuit Data
for board level connections.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Section 10.3
1-5