PNX1502E,557 NXP Semiconductors, PNX1502E,557 Datasheet - Page 561

• Manufacturer Part Number: PNX1502E,557
• Description: IC MEDIA PROC 300MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1502E,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.23 V ~ 1.37 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 935274744557; PNX1502E; PNX1502E

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
2.3.4 Bandwidth and Latency Requirements
The format in memory for both little and big-endian byte ordering is shown in
Normally, the rate of transmission of frames corresponds exactly to the source
sampling frequency. The maximum latency requirement will be for 96 kHz streams
(i.e. frame rate = 96 kHz) with the SPDIF Input input set up for any of the 32-bit
capture modes:
(96K frames/sec) x (8bytes/ frame) = 0.768Mbytes/sec
The maximum latency allowed in order to sustain this transfer rate is (assuming data
transfers are 64 bytes each):
64 bytes/N sec= 0.768 Mbytes/sec
Solving for N and providing a relation,
For error-free operation during sustained DMA, there needs to be one 64 byte DMA
write transfer completed to memory every 83 usecs. This guarantees the latency
requirement for the worst case input sample rate. If the latency requirement is not
met, the hardware sets the HBE bit in the SPDI_STATUS register to logic ‘1’
indicating a bandwidth error. For this condition, one or more audio samples have
been lost and are not recoverable. The bus arbitration for the SPDIF Input input block
should be adjusted by the user to satisfy this latency requirement. Refer to section
Section 3.2
N 83.33uSec
Figure 5:
Note: n, n+1, n+2, n+3 refer
to increasing byte addresses
within a naturally aligned 32-bit
memory address. (i.e. n = 0x0,
0x4, 0x8,0xC, etc.)
R: Right
L: Left
for details on SPDI_STATUS and other registers.
Endian Mode Byte Address Memory Format
Rev. 3 — 17 March 2006
16-bit Stereo
16-bit Stereo
32-bit Stereo
32-bit Stereo
or raw
Little Endian
or raw
Big Endian
Little Endian
Big Endian
31
31
31
31
msbyte
lsbyte
n+3
n+3
msbyte
n+3
n+3
lsbyte
R
R
L
L
lsbyte
msbyte
n+2
n+2
lsbyte
msbyte lsbyte
n
n
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
0
0
PNX15xx Series
15
15
n+7
n+7
msbyte
31
31
Chapter 18: SPDIF Input
n+1
n+1
lsbyte
msbyte
L
L
R
R
msbyte
lsbyte
n
n
n+4
lsbyte
n+4
msbyte
Figure 5
0
0
0
0
etc.
etc.
etc.
etc.
(14)
18-5