PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 135

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

PEB 20534
PEF 20534
Serial Communication Controller (SCC) Cores
blocks or higher but single characters not exceeding the threshold are also forwarded to
the central RFIFO after time out. A time out condition is detected if the line idle time
exceeds a programmable time period (see register CCR1 bit field ’TOLEN’).
Mention that any ’RFRD’ command generated by write access to register CMDR or
automatically by time out mechanism in ASYNC/BISYNC modes always forces a
’frame end/block end’ condition (FE=’1’) causing the DMA controller to finish the current
receive descriptor.
If the SCC receive FIFO is completely filled further incoming data is ignored and a
receive data overflow condition (RDO) is detected. As soon as the receive FIFO provides
empty space receive data is accepted again waiting for a frame end or frame abort
sequence. The automatically generated receive status byte (RSTA) will contain an RDO
indication in this case and the next incoming frame will be received in a normal way.
Therefore no further CPU intervention is necessary to recover the SCC from an RDO
condition.
A "frame" with RDO status might be a mixture of a frame partly received before the RDO
event occured and the rest of this frame received after the receive FIFO again accepted
data and the frame was still incoming. A quite arbitrary series of data or complete frames
might get lost in case of an RDO event. Every frame which must be completely discarded
because of an RDO condition generates an RFO interrupt.
The SCC receive FIFO can be cleared by command ’RRES’ in register CMDR. Note that
clearing the receive FIFO during operation might delete a frame end / block end
indication. A frame which was already partly transferred to the central RFIFO cannot be
"closed" in this case because the DMA controller will not get the corresponding frame
end indication. A new frame received after receiver reset command will be appended to
this "open" frame.
In ASYNC and BISYNC protocol modes, a frame end / block end indication can be forced
by command ’RFRD’ in register CMDR to avoid this unexpected behaviour.
Data Sheet
135
2000-05-30