PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 392

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
FI
ERR
Frame Indication interrupt
This bit indicates that an Frame Indication (FI) interrupt occured.
Receive direction:
FI=’1’ indicates, that a frame has been received completely or was
stopped by a DMAC receiver reset command or a hold condition set in a
receive descriptor. It is set when the DSCC4 branches from the last
descriptor belonging to the current frame (or block) (FE=’1’) to the first
descriptor of a new frame. It is also set when the descriptor in which the
frame/block is finished contained a hold condition.
Transmit direction:
Issued if the ’FE’ bit is detected in the transmit descriptor. It is set when
the DSCC4 branches to the next transmit descriptor, belonging to a new
frame or when ’HOLD’ bit is set in conjunction with ’FE’ bit. Only ’ERR’
indication without ’FI’ is set, if a transmit descriptor contains a ’HOLD’
(hold condition) but no ’FE’ bit.
FI=’0’
FI=’1’
ERROR Indication interrupt
This bit indicates that an Error interrupt occured.
Receive direction:
Issued if the current frame/block could not be transferred to the shared
memory completely, because of a hold condition in a receive descriptor
not providing enough bytes for the frame/block or the frame/block was
aborted by a DMAC receiver reset command.
Transmit direction:
Issued if a transmit descriptor contains a hold condition but FE=’0’ or if
the last descriptor had NO=0 and FE=’0’.
ERR=’0’
ERR=’1’
No Frame Indication (FI) interrupt is indicated by this
vector.
An Frame Indication (FI) interrupt is indicated by this
vector.
No Error (ERR) interrupt is indicated by this vector.
An Error (ERR) interrupt is indicated by this vector.
392
Host Memory Organization
(Rx/Tx Channel)
(Rx/Tx Channel)
PEB 20534
PEF 20534
2000-05-30