PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 155

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

7.4.3
The SCC offers the advantage of recovering the received clock from the received data
by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock
information via a separate serial clock line. For this purpose, the DPLL is supplied with
a ‘reference clock’ from the BRG which is 16 times the expected data clock rate (clock
mode 2, 3a, 6, 7a). The transmit clock may be obtained by dividing the output of the BRG
by a constant factor of 16 (clock mode 2b, 6b; bit ’SSEL’ in register CCR0 set) or also
directly from the DPLL (clock mode 3a, 7a).
The main task of the DPLL is to derive a receive clock and to adjust its phase to the
incoming data stream in order to enable optimal bit sampling.
The mechanism for clock recovery depends on the selected data encoding (see
Encoding” on Page
The following functions have been implemented to facilitate a fast and reliable
synchronization:
Interference Rejection and Spike Filtering
Two or more edges in the same directional data stream within a time period of 16
reference clocks are considered to be interference and consequently no additional clock
adjustment is performed.
Phase Adjustment (PA)
Referring to
the data stream within the PA fields of the time window, the phase will be adjusted by 1/
16 of the data.
Phase Shift (PS) (NRZ, NRZI only)
Referring to
PS field of the time window, a second sampling of the bit is forced and the phase is
shifted by 180 degrees.
Note: Edges in all other parts of the time window will be ignored.
This operation facilitates a fast and reliable synchronization for most common
applications. Above all, it implies a very fast synchronization because of the phase shift
feature: one edge on the received data stream is enough for the DPLL to synchronize,
thereby eliminating the need for synchronization patterns, sometimes called preambles.
However, in case of extremely high jitter of the incoming data stream the reliability of the
clock recovery cannot be guaranteed.
Data Sheet
Clock Recovery (DPLL)
Figure
Figure 52
52,
162).
in the case where an edge appears in the data stream within the
Figure 53
and
Serial Communication Controller (SCC) Cores
Figure
155
54, in the case where an edge appears in
PEB 20534
PEF 20534
2000-05-30
“Data