PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 225

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Table 42
Data Sheet
Bit
Location
31
30
29
28
27
26..25
24
23
Symbol
DPE
SSE
RMA
RTA
0
01
DPED
1
B
B
Status and Command register bits
B
Detected Parity Error
This bit is set by the device whenever it detects a parity error,
even if parity error handling is disabled (as controlled by bit 6
in the Command register).
Signaled System Error
This bit will be set when
• the SERR (SERRE) Enable bit is set in the Command
and
one of the following events occured:
1. A transaction in which the DSCC4 acts as a master is
2. A transaction in which the DSCC4 acts as a master is
3. The transaction has an address parity error and the Parity
Received Master Abort
This bit is set whenever the DSCC4 aborts a transaction with
master abort. This occurs when no device responds.
Received Target Abort
This bit is set whenever a device responds to a master
transaction of the DSCC4 with a target abort.
Signaled Target Abort
The DSCC4 will never signal “Target Abort”.
DEVSEL Timing
The DSCC4 is a medium device.
Data Parity Error Detected
This bit is set when the following three conditions are met:
1. the device asserted PERR itself or observed PERR
2. the device setting the bit acted as the bus master for the
3. and the Parity Error Response bit is set in the Command
Fast Back-to-Back Capable
The DSCC4 is fast Back-to-Back capable.
Description
register
terminated with master abort.
terminated with target abort by the involved target.
Error Response bit is set.
asserted;
transaction in which the error occurred;
register.
225
Detailed Register Description
PEB 20534
PEF 20534
2000-05-30