PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 302

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

Data Sheet
PRE(7..0)
EPT
NPRE(1..0)
ITF
Preamble
This bit field determines the preamble pattern which is send out during
preamble transmission.
Note: In HDLC-mode, zero-bit insertion is disabled during preamble
Enable Preamble Transmission
This bit enables preamble transmission. The preamble is started after
interframe timefill (ITF) transmission is stopped because a new frame is
ready to be transmitted. The preamble pattern consists of 8 bits defined
in bit field ’PRE(7..0)’ which is send repetitively. The number of
repetitions is determined by bit field ’PRE(1..0)’:
EPT=’0’
EPT=’1’
Note: Preamble operation does NOT influence HDLC shared flag
Number of Preamble Repetitions
This bit field determines the number of preambles transmitted:
PRE = ’00’
PRE = ’01’
PRE = ’10’
PRE = ’11’
Interframe Time Fill
This bit selects the idle state of the transmit pin TxD:
ITF=’0’
ITF=’1’
Note: It is recommended to clear bit ’ITF’ in bus configuration modes, i.e.
transmission.
transmission if enabled.
continuous ones are send as idle sequence and data encoding is
NRZ.
Preamble transmission is disabled.
Preamble transmission is enabled.
1 preamble.
2 preambles.
4 preambles.
8 preambles.
Continuous logical ’1’ is send during idle phase.
Continuous flag sequences are sent (’01111110’ flag
pattern).
302
Detailed Register Description
(hdlc/bisync modes)
(hdlc/bisync modes)
(hdlc/bisync modes)
(hdlc/bisync modes)
PEB 20534
PEF 20534
2000-05-30