PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 62

• Manufacturer Part Number: PEB20534H-10V2.1
• Description: Communication Controller 208-Pin FQFP
• Manufacturer: Infineon Technologies

The following table provides an overview of all DMA Controller commands. For detailed
register description refer to
Table 11
Offset
Addr.
0000
Data Sheet
H
Access
Type
r/w
Bit-Fields
Pos.
31..28
27..24
21
20
13..10
9
0
DMAC Commands
Controlled
by
CPU
Name
CFGIQ-
SCCiRX
and
CFGIQ-
SCCiTX
and
CFGIQ
CFG,
CFGIQP
TXPRi
IM
AR
Chapter
Reset
Value
00000200
Default
0
0
1
0
10.
62
H
Register Name
GCMDR:
Global Command Register
Description
Configure Interrupt Queue:
These command bits cause the DMAC to
establish or re-configure the dedicated
interrupt queue using the values of the
corresponding base address registers
and interrupt queue length registers.
(only performed if action request bit ’AR’
is set additionally)
Transmit Poll Request Channel i:
If the DMA transmit channel is stopped
on a HOLD condition (HOLD bit
detected), this command forces a read
transaction on the transmit descriptor
verifying the HOLD condition again.
Interrupt Mask:
If
acknowledge interrupt is supressed.
Action Request:
This bit causes the DMAC to execute all
commands set in registers GCMDR and
CHiCFG.
set
DMA Controller and Central FIFOs
to
’1’
the
action
(Page
PEB 20534
PEF 20534
2000-05-30
request
232)