PEB20534H-10V2.1 Infineon Technologies, PEB20534H-10V2.1 Datasheet - Page 202

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PEB20534H-10V2.1

Manufacturer Part Number
PEB20534H-10V2.1
Description
Communication Controller 208-Pin FQFP
Manufacturer
Infineon Technologies
Datasheets

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Part Number:
PEB20534H-10V2.1
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PEB 20534
PEF 20534
Reset and Initialization Procedure
Software Reset
Software reset control bits are also available to reset single sections of the DSCC4.
Reset of
– DMA receiver is performed via CHiCFG.RDR bit (channel specific)
– DMA transmitter is performed via CHiCFG.RDT bit (channel specific)
– transmitter in SCC is performed via CMDR.XRES bit (channel specific)
– receiver in SCC is performed via CMDR.RRES bit (channel specific)
– EBC (LBI, SSC, GPP) block is performed via LCONF.EBCRES bit.
Note: The software reset only affects the internal state machines. The registers are not
reset.
Data Sheet
202
2000-05-30

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